The present disclosure relates to field effect transistors, and more particularly to field effect transistors made of nitride semiconductors.
A general formula of group III-V nitride semiconductors (e.g., gallium nitride (GaN) etc.) is expressed as InxAlyGa1-x-yN (0≦x≦1, 0≦y≦1). The group III-V nitride semiconductors have wider band gaps, and for example, a band gap of GaN is 3.4 eV at room temperature. The group III-V nitride semiconductors have high breakdown field strength and high saturated electron velocity. Of the group III-V nitride semiconductors, in particular, in a nitride semiconductor having a heterostructure in which an AlGaN layer having a plane (0001) as a main surface is laminated on a GaN layer, electrons are accumulated at a high concentration near the heterojunction interface of the GaN layer due to strong polarization field to generate so-called two-dimensional electron gas. The two-dimensional electron gas is spatially separated from donor impurities added into the AlGaN layer, and thus, has high electron mobility. Furthermore, so-called saturated drift velocity is high in GaN materials. For example, in a high electric field region of about 1×105 V/cm, GaN materials have electron velocity twice or more as high as that of GaAs materials, which are now in the market as materials for high frequency transistors. The GaN materials have high band gaps and high breakdown field strength, and therefore, applications of such materials to high frequency and high output devices has been expected, and such applications have been actively researched and developed.
Trap levels (surface states) with a high density exist on a surface of the group III-V nitride semiconductors, and therefore, when the transistor is operated at a large signal level, the surface is negatively charged due to the response between electrons and the trap levels. When the surface is negatively charged, so-called current collapse occurs, where the drain current decreases and the parasitic resistance increases. When current collapse becomes more pronounced, the drain current decreases and the parasitic resistance increases at a time of driving the transistor by a high voltage, resulting in limiting the power. In order to reduce current collapse, it is important to reduce surface states, and it has been considered that field effect transistors made of group III-V nitride semiconductors include silicon nitride (SiN) as an interlayer film or a surface passivation film to reduce surface states (for example, see A. V. Vertiatchikh, L. F. Eastman, W. J. Schaff and T. Prunty, “Effect of surface passivation of AlGaN/GaN heterostructure field-effect transistor”, Electronics Letters, Vol. 38, 388-389 (2002)). However, even if a SiN film is used as an interlayer film etc., current collapse cannot be completely prevented. Moreover, the formation of an interlayer film made of an SiN film causes problems, e.g., a decrease in the breakdown voltage, an increase in the gate leakage current in a gate electrode. In a field which requires a high output power operation, it is necessary to achieve not only large current control and high breakdown voltage, and therefore, a decrease in the breakdown voltage is a serious problem.
In order to improve breakdown voltages of field effect transistors, it has been considered to provide a gate electrode with a field plate protruding toward a drain electrode (for example, see Japanese Patent Publication No. 2004-200248). The field plate is provided in the gate electrode, whereby it is expected to reduce the concentration of an electric field near the gate electrode, and improve the breakdown voltage. However, when the field plate is provided in the gate electrode, the feedback capacitance increases due to the parasitic capacitance directly under the field plate, and the gain is further reduced than that in a gate electrode having no field plate.
In order to prevent reducing the gain due to a field plate, it has been considered to electrically connect a field plate formed between a gate electrode and a drain electrode to a source electrode (for example, see Japanese Translation of PCT International Application No. 2007-537593). The field plate formed between the gate electrode and the drain electrode is electrically connected to the source electrode, whereby it is expected to be able to reduce the concentration of an electric field near the gate electrode, and decrease the parasitic capacitance (Cgd) occurring between the gate and the drain. With such a configuration, reduced current collapse, improved gate breakdown voltage, and improved gain are expected.